1. Field of the Invention
The present invention relates to a liquid crystal display, and more particularly, to a data driving apparatus and method for a liquid crystal display wherein data lines can be driven on a time division basis to reduce the number of data driver integrated circuits.
2. Discussion of the Related Art
In general, a liquid crystal display (LCD) controls a light transmittance of a liquid crystal by using an applied electric field in order to display an image (picture). The LCD includes a liquid crystal display panel-having liquid crystal cells arranged in a matrix type, and a driving circuit for driving the liquid crystal display panel. The liquid crystal display panel includes gate lines and data lines arranged to cross each other, and each liquid crystal cell is positioned where the gate lines cross the data lines. The liquid crystal display panel is provided with a pixel electrode and a common electrode for applying an electric field to each of the liquid crystal cells. Each pixel electrode is connected to a corresponding one of the data lines via source and drain electrodes of a thin film transistor, which functions as a switching device. The gate electrode of the thin film transistor is connected to a corresponding one of the gate lines, thereby allowing a pixel voltage signal to be applied to the pixel electrodes for each corresponding data line.
The driving circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, and a common voltage generator for driving the common electrode. The gate driver sequentially applies a scanning signal to each of the gate lines in order to sequentially drive the liquid crystal cells on the liquid crystal display panel one gate line at a time. The data driver applies a data voltage signal to each of the data lines whenever the gate signal is applied to any one of the gate lines. The common voltage generator applies a common voltage signal to the common electrode. Accordingly, the LCD controls a light transmittance by application of an electric field between the pixel electrode and the common electrode in accordance with the data voltage signal for each liquid crystal cell, thereby displaying an image. The data driver and the gate driver are incorporated into a plurality of integrated circuits (IC's). The integrated data driver IC and gate driver IC are mounted in a tape carrier package (TCP) to be connected to the liquid crystal display panel by a tape automated bonding (TAB) system, or mounted in the liquid crystal display panel by a chip on glass (COG) system.
FIG. 1 schematically shows a data driving block of an LCD according to the conventional art. In FIG. 1, a data driving block includes data driving IC's 6 connected to a liquid crystal display panel 2 via data TCP's 4, and gate driving IC's 9 connected to gate lines of the liquid crystal display panel 2 via gate TCP's 8. The gate TCP's 8 mounted with the gate driving IC's 9 are electrically connected to gate pads provided at one side of the liquid crystal display panel 2. The gate driving IC's 9 apply a gate signal (scanning signal) to the gate lines of the liquid crystal display panel 2. The data TCP's 4 mounted with the data driving IC's 6 are electrically connected to data pads provided at an upper portion of the liquid crystal display panel 2. The data driving IC's 6 convert digital pixel data signals into analog pixel voltage signals and apply the analog pixel voltage signals to the data lines of the liquid crystal display panel 2.
FIG. 2 is a detailed block diagram showing a configuration of the data driving integrated circuit in FIG. 1. In FIG. 2, each of the data driving IC's 6 includes a shift register part 14 for applying a sequential sampling signal, a latch part 16 for sequentially latching and outputting a pixel data VD in response to the sampling signal, a digital-to-analog converter (DAC) 18 for converting the pixel data VD from the latch part 16 into a pixel signal, and an output buffer part 26 for buffering and outputting the pixel signal from the DAC 18. Furthermore, each of the data driving IC's 6 includes a signal controller 10 for interfacing various control signals from a timing controller (not shown) and the pixel data VD, and a gamma voltage part 12 for supplying positive and negative gamma voltages required in the DAC 18. Each of the data driving IC's 6 drives an n-number of data lines D1 to Dn.
The signal controller 10 controls various control signals (SSP, SSC, SOE, REV and POL) and the pixel data VD to output the control signals and pixel data VD to various corresponding elements. The gamma voltage generator part 12 sub-divides several gamma reference voltages generated from a gamma reference voltage generator (not shown) for each gray level, and outputs signals to the DAC 18.
The shift register part 14 includes a plurality of shift registers that sequentially shift a source start pulse SSP that is received from the signal controller 10 in response to a source sampling clock signal SSC, and output the source start pulse SSP as a sampling signal.
The latch part 16 sequentially samples the pixel data VD received from the signal controller 10 in response to the sampling signal received from the shift register part 14 to latch the pixel data VD. Accordingly, the latch part 16 comprises an n-number of latches for latching an n-number of the pixel data VD, wherein each of the n-number of latches has a size corresponding to a bit number (i.e., 3 bits or 6 bits) of the pixel data VD. Subsequently, the latch part 16 simultaneously outputs an n-number of pixel data VD in response to a source output enable signal SOE received from the signal controller 10.
The DAC 18 simultaneously converts and outputs the pixel data VD received from the latch part 16 into positive and negative pixel signals. Accordingly, the DAC 18 includes a positive (P) decoding part 20 and a negative (N) decoding part 22 that are both commonly connected to the latch part 16, and a multiplexor (MUX) 24 for selecting output signals of the P decoding part 20 and the N decoding part 22. The P decoding part 20 includes P decoders that convert the n-number of pixel data simultaneously input from the latch part 16 into positive pixel signals in combination with the positive gamma voltages output from the gamma voltage part 12. The N decoding part 22 includes N decoders that convert the n-number of pixel data simultaneously input from the latch part 16 into negative pixel signals in combination with the gamma voltages output from the gamma voltage part 12. The multiplexor 24 responds to a polarity control signal POL received from the signal controller 10 to selectively output either one of the positive pixel signals received from the P decoding part 20 or the negative pixel signals received from the N decoding part 22.
The output buffer part 26 includes an n-number of output buffers that comprise voltage followers connected in series to the n-number of data lines D1 to Dn. The n-number of output buffers buffer the pixel voltage signals received from the DAC 18, and applies the buffered pixel voltage signals to the n-number of data lines D1 to Dn.
Accordingly, each of the data driving IC's 6 according to the conventional art require a 2n-number of decoders in addition to an n-number of latches, multiplexors and output buffers in order to drive the n-number of data lines D1 to Dn. As a result, the data driving IC's 6 according to the conventional art have a complex configuration, and hence a manufacturing cost that is 20% to 30% of the total manufacturing cost of a liquid crystal display module.